Successive approximation is one of the techniques used for analog-to-digital conversion. The general functionality and operation of successive approximation register (SAR) analog-to-digital converters (ADCs) is well known in the art. SAR ADCs compare the analog input voltage to reference signal levels, which can be generated by a digital-to-analog converter (DAC). During a first clock cycle, the sampled input voltage may be compared to half the reference signal output by the DAC. If the result of the comparison indicates that the input voltage is greater than half the reference signal, then a respective bit decision relating to the most significant bit (MSB) is made. During the next clock cycle, the input voltage is compared to three quarters or one quarter of the reference signal in accordance with the preceding MSB decision, and a further bit decision is made relating to the next less significant bit. The conversion procedure carries on accordingly, and the DAC output voltage converges successively to the analog input voltage, while evaluating one bit during each clock cycle. The SAR ADC is arranged such that, when the conversion is completed, the digital number input to the DAC represents the digitized input voltage.
Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a conventional SAR ADC. The SAR ADC 100 comprises an ADC stage that is coupled to a SAR controller 102. The ADC stage generally includes a conventional CDAC 102 and comparator 104. The CDAC 102 has a positive side with sampling capacitors CP1 to CPN and a negative side with sampling capacitors CM1 to CMN. The capacitors CP1 and CM1 are adapted to evaluate the most significant bit or MSB and the capacitors CPN and CMN are adapted to evaluate the least significant bit or LSB. The common nodes of each of the capacitors CP1 to CPN and CM1 to CMN can be coupled to a common mode voltage VCM by sample and hold switches SCM1 and SCM2 and each respective input of comparator 104. The other side of each of the capacitors CP1 to CPN and CM1 to CMN can be coupled to a positive reference signal REFP, a negative reference signal REFM or a differential input signal INP and INN.
The analog input voltage can be sampled directly on the capacitors CP1 to CPN and CM1 to CMN by opening the switches SCM1 and SCM2 and coupling the inputs for signal INP and INN to the other side of some are all capacitors, such that a charge corresponding to the size of the capacitors and proportional to the amplitude of the input voltage is present on the sampling capacitors. The sampled charge is redistributed stepwise among the capacitors of the CDAC 102. The magnitude of the input voltage is basically determined by selectively and consecutively switching the other sides of the capacitors between the different reference signal levels REFP and REFM and comparing the established voltage level on the common nodes. The switching of the other side of each of the plurality of capacitors is performed through numerous switches SM1 to SMN and SP1 to SPN, which are controlled by control signals provided by control stage 106 in response to the output of comparator 104 at each step of the conversion process. The capacitors having the largest capacitance CP1 and CM1 will be the first to be coupled to a specific reference signal level, while the remaining capacitors CP2 to CPN and CM2 to CMN are coupled to another reference signal level. Then the voltage on the common nodes, which are coupled to respective positive and negative inputs of a comparator 104, is compared, and the output of the comparator 104 represents the bit values of the digital output word DOUT bit by bit, starting with the most significant bit. In accordance with the signal at the output of the comparator 104 (i.e., the comparison result), the capacitors CP1 to CPN and CM1 to CMN are consecutively coupled one-by-one to either the first or the second reference signal level REFP or REFM and remain in the position during the subsequent conversion steps. The intermediate results are stored in a register (successive approximation register) which resides together with other logic for controlling the analog-to-digital conversion process in a control stage referred to as successive approximation register or SAR controller 106. The controller 106 may have an input for receiving a clock signal CLK and an input for receiving a start signal START which indicates that conversion is to be started. The controller 106 provides the digital output word which represents the digital value of the sampled input voltage at output node DOUT.
Up-to-date electronic devices, and corresponding semiconductor manufacturing processes, typically use supply voltages of 5V or less in order to save power and to gain speed. The supply voltage limits the input signal range of the ADCs. In order to convert a +/−10V input signal, which is a typical industrial standard, the signal is divided either with a resistive divider or with a capacitive divider, so as to fit the input signal voltage range into the comparator's input voltage range, which can basically be between ground and the supply voltage level. However, the division of the input signal decreases the signal-to-noise ratio (SNR) of the ADC. With a 5V supply voltage range and an input range of, for example, +/−10V (i.e., a division by 4 is required for an input range of +/−10V), the LSB of a 16 bit converter corresponds to 76 μV, although it could amount to 305 μV if the signal was not divided. The input range could also be +/−5V or +/−12V, etc., for example. A typical up-to-date 16 bit SAR ADC has a noise level that corresponds to 2 to 6 LSBs at the output for any DC input voltage. In order to handle the relatively large input voltage range, high-voltage transistors are required. Typical 5V semiconductor manufacturing processes provide high-voltage transistors so that ADCs are available that have a high input voltage range even on a low voltage core that runs, for example, with the 5V supply voltage. However, dividing the input signal is always necessary, thereby decreasing the achievable SNR.